1. Field
Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to drivers for providing multi-mode clock signals for electronic devices.
2. Description of the Related Technology
Certain electronic systems use clock signals for various tasks. Each of these tasks may have individual specifications regarding the frequency and tolerances in logic thresholds. Some tasks may accommodate relaxed rise and fall times and be satisfied with approximate logic levels during operation, while others will require strict adherence to timing standards. Furthermore, some tasks employ different logic standards from other tasks. Examples of such different logic standards include low voltage differential signaling (LVDS), positive emitter-coupled logic (PECL), low-voltage positive emitter-coupled logic (LVPECL), and complementary metal-oxide-semiconductor (CMOS) logic.
In many of these electronic systems, such different tasks may need to be synchronized with one another. Thus, such electronic systems may generate a single master clock, and employ internal circuit logic to produce multiple clock signals based on the master clock for each of the various needs. This scheme generally requires additional circuitry to generate each of the varied clock signals.
FIG. 1 is a block diagram of an electronic system 100 in which multiple clock signals are produced for the operation of various components. The illustrated electronic system includes a master clock generator 101, a clock generator/distributor 103, and a plurality of components 105a-105d. In some embodiments, the electronic system 100 may form at least part of, for example, a wireless transmission/reception base station or an optical transmission system.
The master clock generator 101 generates a master clock signal CLK for the clock generator/distributor 103. The clock generator/distributor 103 cleans up and modifies the master clock signal CLK to produce a plurality of clock signals CLK1-CLKn, and supplies the clock signals CLK1-CLKn to the components 105a-105d of the system.
The clock signals CLK1-CLKn may be generally synchronized with the master clock signal CLK. However, one or more of the clock signals CLK1-CLKn may have a different frequency and/or voltage level from those of the master clock signal CLK, depending on the needs of the components 105a-105d that receive the clock signals CLK1-CLKn. Further, some of the clock signals CLK1-CLKn may have different frequencies and/or characteristics from one another, depending on the needs of the components 105a-105d. 
Referring to FIGS. 2A-2C, various conventional configurations of a clock generator/distributor will be described as follows. FIG. 2A illustrates a clock generator/distributor 103a. The illustrated clock generator/distributor 103a serves to generate and distribute clock signals CLK1-CLKn. The clock generator/distributor 103a may include a phase-locked loop (PLL) 203, a plurality of clock dividers 201a-201d, and a plurality of drivers 202a-202d. 
The phase-locked-loop (PLL) 203 is configured to receive a master clock signal CLK. The PLL 203 serves to produce a refined clock signal CLK_B with reference to the master clock signal CLK, and provide the refined clock signal CLK_B to the clock dividers 201a-201d. In certain embodiments, multiple phase-locked loop stages may be cascaded together within the clock generator/distributor 103a prior to providing a clock signal CLK_B to the dividers 201a-201d. In some embodiments, a first PLL may have a narrow loop bandwidth providing initial jitter cleanup of the input reference signal. A second PLL may have a frequency multiplying and/or dividing PLL that converts the first stage output frequency to a selected frequency. A skilled artisan will thus appreciate that various configurations of PLL can be used for the PLL 203.
Each of the clock dividers 201a-201d serves to divide the refined clock signal CLK_B into a clock signal that has the same or a lower frequency. For example, if the refined clock signal CLK_B has a frequency f, the clock dividers 201a-201d can generate clock signals having a frequency of, for example, f, f/2, f/4, or f/8. The clock dividers 201a-201d may provide their divided clock signals to the drivers 202a-202d. 
The drivers 202a-202d may buffer the divided clock signals, and may also modify the characteristics of the divided clock signals. The drivers 202a-202d provide the buffered and/or modified clock signals CLK1-CLKn to various electronic components. In the context of this document, the amplified and/or modified clock signals CLK1-CLKn may be referred to as “component clock signals.”
FIG. 2B illustrates another configuration for a clock generator/distributor 103b. The illustrated clock generator/distributor 103b serves to divide and distribute clock signals. The clock generator/distributor 103b includes an amplifier 205, a plurality of clock dividers 201a-201d, and a plurality of drivers 202a-202d. 
The amplifier 205 is configured to receive and amplify (i.e. level shift) a master clock signal CLK, and provides a resulting clock signal CLK_B to the clock dividers 201a-201d. The configurations of the clock dividers 201a-201d and the drivers 202a-202d can be as described above in connection with FIG. 2A.
FIG. 2C illustrates another configuration for a clock generator/distributor 103c. The illustrated clock generator/distributor 103c serves to distribute and fan out clock signals having the same frequency. The clock generator/distributor 103c includes an amplifier 205 and a plurality of drivers 202a-202d, but does not include clock dividers. The amplifier 205 is configured to receive and amplify a master clock signal CLK, and provides an amplified master clock signal CLK_B to the drivers 202a-202d. Other details of the amplifier 205 and the drivers 202a-202d can be as described above in connection with FIG. 2B.
In some instances, a clock generator/distributor needs to provide different clock signals to various components of an electronic system. For example, the different clock signals may need to be in compliance with different logic standards that the components use. In such instances, one or more of the drivers of the clock generator/distributor may have different circuit configurations, each specified for a particular standard.
However, in certain instances, one or more of the drivers of a clock generator/distributor may have the same configuration that can be configured to provide such different clock signals. For example, each of the drivers can have the same circuit that is configurable to provide different clock signals in response to control signals. Such a driver may be referred to as a “multi-mode driver” in the context of this document.
Certain drivers for a clock generator/distributor are known to be configurable to provide clock signals complying with two or more of different logic standards, for example, low voltage differential signaling (LVDS), positive emitter-coupled logic (PECL), low-voltage positive emitter-coupled logic (LVPECL), and complementary metal-oxide-semiconductor (CMOS) logic.